Calls for papers
International Journal of Circuits and Architecture Design
Special Issue on: "Challenges to IC Design in the 21st Century"
Dr. P. Karthigaikumar, Karpagam College of Engineering, India
Dr. Anand Paul, Kyungpook National University, South Korea
As process technology advances to 20nm and beyond, design complexity dramatically increases due to many challenging design considerations such as 3D integration, chip-package-board co-design, FinFET or 3D transistors, engineering change order (ECO), inter-die/intra-die variation, quality-ensured analogue and mixed-signal layouts, thermal effects, signal integrity, sub-wavelength lithography and ultra-low-power design. As a result, there is a need to investigate and deliver new VLSI design methodologies, algorithms and tools for addressing nanometer design challenges.
Power efficiency is also becoming a major concern in all areas of VLSI design and processing. The challenge for more power-efficient chips and systems arises at every level of design and production. Power consideration has already been seen in the following aspects: software, architecture, systems, CAD, logic, circuits, devices, processing and materials.
The special issue will deal with all aspects of new technical breakthroughs in VLSI design. It is our intention to promote cross-fertilisation between VLSI design and processing technology. All papers are encouraged to discuss the impact and relationship of their technologies/ideas/methods with other aspects of chip production. For example, a new low-power circuit structure may warrant a discussion of the advantages or difficulties of the specific techniques in relation to the reliability, testing and feasibility of mass production.
The issue will carry revised and substantially extended versions of selected papers presented at the 3rd International Conference on Electronics and Communication systems (ICECS 2016), but we also strongly encourage researchers unable to participate in the conference to submit articles for this call.Subject Coverage
Suitable topics include, but are not limited to, the following:
- Power-efficient computations, architectures and systems
- Power-efficient design techniques
- Design and implementation considerations for low-power chips
- Low-power logic implementations
- Low-power circuit structures
- Low-power devices
- Low-power processes and material.
- Cell library design and analysis for FinFET or new device structures
- 2D and 3D floorplanning, partitioning, placement and routing
- CAD for analogue, mixed-signal and RF layouts
Notes for Prospective Authors
Submitted papers should not have been previously published nor be currently under consideration for publication elsewhere. (N.B. Conference papers may only be submitted if the paper has been completely re-written and if appropriate written permissions have been obtained from any copyright holders of the original paper).
All papers are refereed through a peer review process.
All papers must be submitted online. To submit a paper, please read our Submitting articles page.
Manuscripts due by: 10 May, 2016
Notification to authors: 15 August, 2016
Final versions due by: 15 September, 2016