International Journal of Intelligent Defence Support Systems
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International Journal of Intelligent Defence Support Systems (2 papers in press)
Program Viewer A Defence Portfolio Capability Management System by Edward Lo, Nicholas Tay, Gary Bulluss Abstract: Information and communications technology (ICT) advancements are modernising Defence, presenting opportunities for improved efficiency and effectiveness in areas including warfighting, logistics and corporate support. With over A$10 billion expended annually by the Australian Defence Organisation (ADO) on major and minor capital acquisitions, small innovations in Defence capability management can reap huge financial benefits. The recent First Principles Review (FPR) has clearly highlighted further need for improvements in Defence capability management. Moreover, improved data management and decision support tools are essential to achieving the efficiencies and realising the opportunities presented. Program Viewer is one such tool that leverages and aggregates actual stakeholder data into a Department of Defense Architecture Framework v2 (DODAF2) / Unified Profile for DoDAF and MODAF (UPDM) compliant data repository to support force posture planning and capability acquisition prioritisation. Key contributions from this paper include (1) fusing disparate and unexploited Defence enterprise data for analysis, (2) producing a range of tailorable and informative views of cost, schedule and capability from actual Defence data, and (3) enabling impact analysis on what-if scenarios. Incorporating numerous stakeholder requested features, Program Viewer offers a new approach to aggregating and analysing Defence capabilities, and has been used to support the current and previous Force Structure Reviews (FSRs). This papers target audience includes ADO and international military systems architects. Keywords: Program Viewer; data analytics; data visualisation; dependency analysis; whole-of-portfolio capability management; DODAF2; UPDM; Capability Acquisition and Sustainment Group; Force Structure Review.
A novel approach to design a digital clock triggered modified pulse latch for 16-bit shift register. by Suraj Pattanaik Abstract: A low power area reduced clock pulse generator and a modified clock sense pulse latch is proposed for conventional shift register. The proposed clock pulse generator basically based on the inverted inverter delay circuit and a pass transistor logic AND gate circuit. This clock pulse generator and modified clock sense pulse latch consumes low power and low area than other conventional clock pulse generator. Here the clock pulse generator consist of five number of back to back cascaded clock pulse circuit. The pulse generated from the proposed clock pulse generator helps to increase the speed, reduces the area and power of conventional shift register. The clock pulse generator and the modified clock sense pulse latch is designed and tested by the Cadence Virtuoso 180nm technology. The power consumption for 16 bit shift register is 0.705mW at 500MHz clock frequency and 0.395mW at 100MHz frequency. The proposed shift register saved 12% area and 19.50% power rather than other conventional shift register. Keywords: low power, clock pulse generator, inverted –inverter, 180nm, cadence virtuoso, complimentary pass transistor logic, area-efficiency, shift register