Article: Power-aware high level evaluation model of interconnect length of on-chip memory network topology Journal: International Journal of Computational Science and Engineering (IJCSE) 2018 Vol.17 No.4 pp.422 - 431 Abstract: Interconnect power is the factor that dominates the power consumption on the on-chip memory architecture. Almost all dedicated wires and buses are replaced with packet switching interconnection networks which have become the standard approach to on-chip interconnection. Unfortunately, rapid advances in technology are making it more difficult to assess the interconnect power consumption of NoC. To resolve this problem, a new evaluating methodology for interconnect power evaluation based on topology of on-chip memory (IP-ETOM) is proposed in this paper. To validate this method, two multicore architectures 2D-mesh and triplet-based architecture (TriBA) are evaluated in this research work. The on-chip memory network model is evaluated based on characteristics of on-chip architecture interconnection. MATLAB is used for conducting the experiment that evaluates the interconnection power of TriBA and 2D-mesh. Inderscience Publishers - linking academia, business and industry through research

Title: Power-aware high level evaluation model of interconnect length of on-chip memory network topology

Authors: Xiao-Jun Wang; Feng Shi; Yi-Zhuo Wang; Hong Zhang; Xu Chen; Wen-Fei Fu

Addresses: School of Computer Science and Technology, Beijing Institute of Technology, Beijing, 100081, China ' School of Computer Science and Technology, Beijing Institute of Technology, Beijing, 100081, China ' School of Computer Science and Technology, Beijing Institute of Technology, Beijing, 100081, China ' School of Computer Science and Technology, Beijing Institute of Technology, Beijing, 100081, China ' School of Computer Science and Technology, Beijing Institute of Technology, Beijing, 100081, China ' School of Computer Science and Technology, Beijing Institute of Technology, Beijing, 100081, China

Abstract: Interconnect power is the factor that dominates the power consumption on the on-chip memory architecture. Almost all dedicated wires and buses are replaced with packet switching interconnection networks which have become the standard approach to on-chip interconnection. Unfortunately, rapid advances in technology are making it more difficult to assess the interconnect power consumption of NoC. To resolve this problem, a new evaluating methodology for interconnect power evaluation based on topology of on-chip memory (IP-ETOM) is proposed in this paper. To validate this method, two multicore architectures 2D-mesh and triplet-based architecture (TriBA) are evaluated in this research work. The on-chip memory network model is evaluated based on characteristics of on-chip architecture interconnection. MATLAB is used for conducting the experiment that evaluates the interconnection power of TriBA and 2D-mesh.

Keywords: power evaluation; on-chip memory network topology; NoC interconnects; IPETOM.

DOI: 10.1504/IJCSE.2018.096030

International Journal of Computational Science and Engineering, 2018 Vol.17 No.4, pp.422 - 431

Received: 01 Jul 2016
Accepted: 09 Aug 2016
Published online: 09 Nov 2018 *

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Title: Power-aware high level evaluation model of interconnect length of on-chip memory network topology

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