Power-aware high level evaluation model of interconnect length of on-chip memory network topology Online publication date: Fri, 09-Nov-2018
by Xiao-Jun Wang; Feng Shi; Yi-Zhuo Wang; Hong Zhang; Xu Chen; Wen-Fei Fu
International Journal of Computational Science and Engineering (IJCSE), Vol. 17, No. 4, 2018
Abstract: Interconnect power is the factor that dominates the power consumption on the on-chip memory architecture. Almost all dedicated wires and buses are replaced with packet switching interconnection networks which have become the standard approach to on-chip interconnection. Unfortunately, rapid advances in technology are making it more difficult to assess the interconnect power consumption of NoC. To resolve this problem, a new evaluating methodology for interconnect power evaluation based on topology of on-chip memory (IP-ETOM) is proposed in this paper. To validate this method, two multicore architectures 2D-mesh and triplet-based architecture (TriBA) are evaluated in this research work. The on-chip memory network model is evaluated based on characteristics of on-chip architecture interconnection. MATLAB is used for conducting the experiment that evaluates the interconnection power of TriBA and 2D-mesh.
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