Title: Analyses of parasitic capacitance effects and flicker noise of the DAC capacitor array for high resolution SAR ADCs

Authors: Xicai Yue; Janice Kiely; Chris McLeod

Addresses: School of Engineering, Design and Mathematics, University of the West of England, Bristol BS16 1QY, UK ' School of Engineering, Design and Mathematics, University of the West of England, Bristol BS16 1QY, UK ' Department of Electrical and Electronic Engineering, Imperial College London, London SW7 2AZ, UK

Abstract: This paper analyses the effects of parasitic capacitances of unit capacitors on the accuracy and the noise performance of the DAC capacitor array in a SAR ADC, showing that thermal noise of the array decreases while gain error is introduced. The gain error is almost independent of the number of bits, but the dynamic range of the high resolution ADC is severely reduced due to the gain error. The post-layout parasitic capacitance analysis of a 10-bit poly-poly array shows a large difference between the top-plate and bottom-plate parasitic capacitances so that the gain error can be decreased by 152 times when top-plates are connected together as the output node of the array. The switching transistors' flicker noise calculation for a 10-bit and an 18-bit SAR ADC shows that flicker noise can be safely ignored for 10-bit 1MSPS SAR, but should be considered for the higher resolution SAR ADCs.

Keywords: SAR; successive approximation register; ADC; DAC capacitor array; parasitic capacitance; thermal noise; flicker noise.

DOI: 10.1504/IJCAT.2018.095934

International Journal of Computer Applications in Technology, 2018 Vol.58 No.4, pp.259 - 266

Received: 24 Jul 2017
Accepted: 24 Jul 2017
Published online: 05 Nov 2018 *

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