Title: An efficient realisation of FIFO buffers for NoC routers using technology dependent optimisations targeting LUT based FPGAs
Authors: Liyaqat Nazir; Roohie Naaz Mir
Addresses: Department of CSE, National Institute of Technology Srinagar, India ' Department of CSE, National Institute of Technology Srinagar, India
Abstract: The communication between processing elements is facing challenges due to power, area and latency. The temporary flit storage blocks needed during communication contributes to the major power and area consumption in Network-on-Chip. Moreover, with modern FPGAs causing a rapid shift from prototype designing to low and medium volume productions, it becomes imperative to consider architectural optimisations that are specific to FPGA fabric only. This article attempts to provide novel optimised FIFO buffer realisation using technology dependent mapping strategies. This will help designers to adopt efficient design of NoC microarchitecture routers. The properties of proposed realisation are studied with a micro-architecture router for several packet flit rates given at an input port. The proposed realisation will help in the elimination of the presence of fixed inherent FIFO buffer instantiations as the proposed realisation gives us an idea to explore underlying FPGA fabric more efficiently for realisation of the FIFO than existing.
Keywords: depth; FIFO; network-on-chip; NoC; flits; traffic.
International Journal of Circuits and Architecture Design, 2016 Vol.2 No.3/4, pp.201 - 232
Received: 26 Oct 2016
Accepted: 21 May 2017
Published online: 05 Feb 2018 *