Authors: Shoba Mohan; Nakkeeran Rangaswamy
Addresses: Department of Electronics Engineering, School of Engineering and Technology, Pondicherry University, Puducherry-605014, India ' Department of Electronics Engineering, School of Engineering and Technology, Pondicherry University, Puducherry-605014, India
Abstract: Designing multiplier with high speed low power and minimal layout structure is of prime importance. In this paper, we propose a new architecture of 8 × 8 Wallace tree multiplier by incorporating 4-2 compressor and full adder during the partial products reduction process. Also, the final carry propagate addition is performed by carry look ahead adder to reduce the delay. Further, the multiplier is implemented using full swing gate diffusion input (GDI) logic. This design is simulated using Cadence virtuoso at 45 nm technology model. The simulation results reveal that the proposed multiplier achieves 23% power reduction than the conventional tree multiplier. Also, a large amount of reduction in wiring head is attained for the proposed multiplier. Further, an analysis of circuit's performance variation with respect to process variations is done by Monte Carlo simulation. The results confirmed that proposed multiplier has more immune against process variation while comparing with existing designs.
Keywords: GDI logic; CLA adder; tree multiplier; power; digital circuit.
International Journal of Circuits and Architecture Design, 2016 Vol.2 No.3/4, pp.183 - 200
Received: 25 Nov 2016
Accepted: 21 May 2017
Published online: 05 Feb 2018 *