Title: Design of PVT compensated current starved ring oscillator

Authors: D. Anitha; K. Manjunatha Chari; P. Satish Kumar

Addresses: Department of ECE, GITAM University, Hyderabad 502329, India ' Department of ECE, GITAM University, Hyderabad 502329, India ' Department of ECE, ACE Engineering College, Hyderabad 500043, India

Abstract: In this paper the design of a 3 stage current starved ring oscillator which is less sensitive to process, supply voltage and temperature variations are presented. The ring oscillator is implemented with a PV insensitive current source and addition-based current source to achieve the PVT compensation. The design methodology for PV insensitive current source and addition-based current source is discussed. These results are compared with the current starved ring oscillator with baseline current source and basic current mirror. Simulation results carried out in GPDK 90 nm shows 64.8% less process, mismatch variation of output frequency in PV insensitive current source RO and 72.22% in addition-based RO compared to that of conventional current starved ring oscillator. Post layout simulation is also performed for addition-based RO as it is providing low power and minimum area.

Keywords: PVT variations; addition-based current source; oscillator design; current starved ring oscillators; PVT compensation; simulation.

DOI: 10.1504/IJCAD.2016.082146

International Journal of Circuits and Architecture Design, 2016 Vol.2 No.2, pp.169 - 181

Accepted: 16 Jul 2016
Published online: 08 Feb 2017 *

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