Title: Fundus image denoising using FPGA hardware architecture

Authors: Amira Hadj Fredj; Mariem Ben Abdallah; Jihene Malek; Ahmad Taher Azar

Addresses: Electronics and Micro-Electronics Laboratory, Monastir University, Tunisia ' Electronics and Micro-Electronics Laboratory, Monastir University, Tunisia ' Electronics and Micro-Electronics Laboratory, Monastir University, Tunisia ' Faculty of Computers and Information, Benha University, Egypt

Abstract: Image processing algorithms, implemented in hardware, have recently emerged as the most viable solution for improving the performance of image processing systems. In this paper, a version of an anisotropic diffusion technique is used to reduce noise from retinal images, namely Speckle Reducing Anisotropic Diffusion (SRAD). The SRAD filter can improve images corrupted by multiplicative or additive noise, but it has been the most computationally complex and it has not been suitable for software implementation in real-time processing. In this paper, an efficient Field-Programmable Gate Array (FPGA)-based implementation of the SRAD filter is presented to accelerate the processing time. A comparison of the most used classical suppression filters like Gaussian, Median, Perona and Malik anisotropic diffusion has been carried out. The experimental results reveal a 38× performance improvement over the original MATLAB implementation and a 1.33× performance improvement over the hardware implementation using the Xilinx System Generator tool.

Keywords: SRAD filter; FPGA; field-programmable gate arrays; parallel architecture; retinal fundus images; fundus image denoising; image processing; anisotropic diffusion; retinal images.

DOI: 10.1504/IJCAT.2016.077791

International Journal of Computer Applications in Technology, 2016 Vol.54 No.1, pp.1 - 13

Received: 02 Mar 2015
Accepted: 13 Mar 2015

Published online: 15 Jul 2016 *

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