Fundus image denoising using FPGA hardware architecture
by Amira Hadj Fredj; Mariem Ben Abdallah; Jihene Malek; Ahmad Taher Azar
International Journal of Computer Applications in Technology (IJCAT), Vol. 54, No. 1, 2016

Abstract: Image processing algorithms, implemented in hardware, have recently emerged as the most viable solution for improving the performance of image processing systems. In this paper, a version of an anisotropic diffusion technique is used to reduce noise from retinal images, namely Speckle Reducing Anisotropic Diffusion (SRAD). The SRAD filter can improve images corrupted by multiplicative or additive noise, but it has been the most computationally complex and it has not been suitable for software implementation in real-time processing. In this paper, an efficient Field-Programmable Gate Array (FPGA)-based implementation of the SRAD filter is presented to accelerate the processing time. A comparison of the most used classical suppression filters like Gaussian, Median, Perona and Malik anisotropic diffusion has been carried out. The experimental results reveal a 38× performance improvement over the original MATLAB implementation and a 1.33× performance improvement over the hardware implementation using the Xilinx System Generator tool.

Online publication date: Fri, 15-Jul-2016

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