Title: Efficient modulo 2n +1 multiplier

Authors: Masoud Abbasi Alaie; Somayeh Timarchi

Addresses: Electrical and Computer Engineering Department, Shahid Beheshti University, G.C., 1983963113, Tehran, Iran ' Electrical and Computer Engineering Department and Cyber Space Institute, Shahid Beheshti University, G.C., 1983963113, Tehran, Iran

Abstract: Modulo 2n + 1 multiplier is one of the critical components in RNS-based cryptography and security application, digital signal processing, and fault-tolerant system. An important issue in multiplication is utilising an efficient reduction tree for partial product accumulation. This paper presents two efficient architectures for modulo 2n + 1 multiplication. The proposed methods realise a well-organised addition tree for partial product reduction that is based on utilising appropriate compressors. The synthesis results depicts that the proposed architectures consume less power and occupy less area than the most efficient modulo 2n + 1 multiplier. The least delay obtained for the proposed architecture is also less than the one achieved for the best modulo 2n + 1 multiplier.

Keywords: computer arithmetic; residue number system; RNS; modulo 2n + 1 multiplier; partial product reduction; compressors; cryptography; security applications; digital signal processing; DSP; fault tolerant systems.

DOI: 10.1504/IJCAET.2016.077604

International Journal of Computer Aided Engineering and Technology, 2016 Vol.8 No.3, pp.260 - 276

Received: 04 Dec 2013
Accepted: 05 Feb 2014

Published online: 07 Jul 2016 *

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