Efficient modulo 2ⁿ +1 multiplier
by Masoud Abbasi Alaie; Somayeh Timarchi
International Journal of Computer Aided Engineering and Technology (IJCAET), Vol. 8, No. 3, 2016

Abstract: Modulo 2ⁿ + 1 multiplier is one of the critical components in RNS-based cryptography and security application, digital signal processing, and fault-tolerant system. An important issue in multiplication is utilising an efficient reduction tree for partial product accumulation. This paper presents two efficient architectures for modulo 2ⁿ + 1 multiplication. The proposed methods realise a well-organised addition tree for partial product reduction that is based on utilising appropriate compressors. The synthesis results depicts that the proposed architectures consume less power and occupy less area than the most efficient modulo 2ⁿ + 1 multiplier. The least delay obtained for the proposed architecture is also less than the one achieved for the best modulo 2ⁿ + 1 multiplier.

Online publication date: Thu, 07-Jul-2016

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