Title: Effects of tool stiffness and infeed scheme on planarisation. (Integrated model for simulation of planarisation process)
Authors: Libo Zhou, Jun Shimizu, Hiroshi Eda
Addresses: Department of Systems Engineering, Ibaraki University, 4-12-1 Nkanarusawa, Hitachi 316-8511, Japan. ' Department of Systems Engineering, Ibaraki University, 4-12-1 Nkanarusawa, Hitachi 316-8511, Japan. ' Department of Systems Engineering, Ibaraki University, 4-12-1 Nkanarusawa, Hitachi 316-8511, Japan
Abstract: The motivation for this work is to understand the effects of tool property and downfeed (or infeed) method on the planarisation of a patterned Si wafer. In the oxide or interlevel dielectric (ILD) planarisation process, the major concerns are the global planarity, oxide thickness differences in different regions across the chip and the remaining local step height (or height differences in oxide over the patterned features and between pattered features). By extending the MIT |density and step| height dependent model, this paper aims to establish an analytical model to incorporate the tool stiffness and infeed scheme. A 3D simulation has also been performed to show the model validity and the effects of tool stiffness and infeed scheme on the planarity of wafer.
Keywords: interlevel dielectric planarisation; effective pattern density; local step height; tool stiffness; infeed scheme; position control; pressure control; silicon wafers; semiconductor manufacturing; global planarity; oxide thickness; simulation; patterned wafers.
International Journal of Manufacturing Technology and Management, 2005 Vol.7 No.5/6, pp.490 - 503
Published online: 02 Sep 2005 *Full-text access for editors Access for subscribers Purchase this article Comment on this article