Title: Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs

Authors: Burhan Khurshid; Roohie Naaz

Addresses: Department of Computer Science and Engineering, National Institute of Technology Srinagar, Jammu and Kashmir, India ' Department of Computer Science and Engineering, National Institute of Technology Srinagar, Jammu and Kashmir, India

Abstract: Modern day field programmable gate arrays (FPGA) have look-up tables (LUT) as inherent basic logic elements. With FPGAs fast moving from prototype designing to low and medium volume productions, there is an increased need for efficient utilisation of these FPGA primitives. Unfortunately, majority of the work concerned with FPGA implementations focus only on the technology independent (architectural) optimisations that can be done at the top level of the logic synthesis process. In this paper, we consider the technology dependent optimisation of the fixed-point bit-parallel multiplier on LUT-based FPGAs. We perform technology dependent optimisations prior to the design entry phase and then use instantiation-based coding styles to ensure that the optimisations remain preserved throughout the synthesis process. Our implementations show substantial improvement in terms of resources utilised, critical path delays and dynamic power dissipation.

Keywords: fixed-point arithmetic; field programmable gate arrays; FPGAs; FPGA primitives; look-up tables; LUT; technology mapping; technology dependent optimisation; bit-parallel multipliers; resource utilisation; critical path delays; dynamic power dissipation.

DOI: 10.1504/IJHPSA.2016.076205

International Journal of High Performance Systems Architecture, 2016 Vol.6 No.1, pp.28 - 35

Received: 18 May 2015
Accepted: 09 Dec 2015

Published online: 29 Apr 2016 *

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