Title: Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

Authors: J.P. Anita; P. Sudheesh

Addresses: Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham University, Coimbatore, India ' Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham University, Coimbatore, India

Abstract: An algorithm of test pattern generation for multiple faults is proposed using the zero suppressed decision diagrams (ZBDDs). Test pattern generation plays a major role in the design and testing of any chip. The proposed ZBDD is generated from its corresponding binary decision diagram (BDD). A test ZBDD is obtained from the true and faulty ZBDDs and the test patterns are generated from the test ZBDD. The obtained patterns are reordered because the order in which these patterns are used to test the chip is immaterial as far as the faults are concerned but the transitions between the test patterns affect the test power. Hence, the primary objective of the proposed work is the generation of test patterns for a given set of multiple faults. The next objective is to reduce the test power which is the power consumed during testing.

Keywords: binary decision diagrams; BDD; zero suppressed decision diagrams; ZBDDs; multiple faults; test pattern generation; reordering algorithm; test power reduction; test patterns; power consumption.

DOI: 10.1504/IJHPSA.2016.076204

International Journal of High Performance Systems Architecture, 2016 Vol.6 No.1, pp.51 - 60

Received: 12 Jun 2015
Accepted: 02 Dec 2015

Published online: 29 Apr 2016 *

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