Title: On the effectiveness of accelerating MapReduce functions using the Xilinx Vivado HLS tool

Authors: Mageda Sharafeddin; Mazen A.R. Saghir; Haitham Akkary; Hassan Artail; Hazem Hajj

Addresses: Department of Electrical and Computer Engineering, American University of Beirut, Beirut, Lebanon ' Department of Electrical and Computer Engineering, American University of Beirut, Beirut, Lebanon ' Department of Electrical and Computer Engineering, American University of Beirut, Beirut, Lebanon ' Department of Electrical and Computer Engineering, American University of Beirut, Beirut, Lebanon ' Department of Electrical and Computer Engineering, American University of Beirut, Beirut, Lebanon

Abstract: Programming FPGAs requires advanced hardware design skills which limits their adoption in data centres. FPGA vendors have provided high level synthesis (HLS) tools to build register transfer level (RTL) specifications from designs provided in high level languages. We present a suite of C and C++-based hardware accelerators for the Purdue MapReduce benchmark suite and use the Xilinx Vivado HLS tool to compare their performance and resource efficiency to hand-coded RTL code. We show that simple design changes in the high level language-based accelerators can improve results. Using Vivado HLS, five benchmarks match the performance of hand optimised RTL while sort, self join, adjacency list and word count algorithms are about 4.7×, 3×, 2× and 1.3× slower, respectively.

Keywords: FPGA; field-programmable gate arrays; hardware accelerators; MapReduce; reconfigurable computing; high level synthesis; HLS; Vivado; register transfer level; RTL specifications.

DOI: 10.1504/IJHPSA.2016.076197

International Journal of High Performance Systems Architecture, 2016 Vol.6 No.1, pp.1 - 12

Received: 25 May 2015
Accepted: 20 Oct 2015

Published online: 29 Apr 2016 *

Full-text access for editors Access for subscribers Purchase this article Comment on this article