Title: Automated physical verification of I/O pads using scaling factors

Authors: Rajesh Mangalore Anand; Soujanya Ravula; Kalpashree Anand

Addresses: Smartplay Technologies, Bangalore, 560066, India ' Infineon Technologies AG, Munich, 85579, Germany ' Infineon Technologies, Bangalore, 560066, India

Abstract: The physical verification process is a vital step in an ASIC chip design flow to enable the mask layouts manufacturable and functional. The input/output (I/O) pads which are at the peripheries of the chip operating at the multi-voltage domains are critical components to be verified during the top-level verification. The proposal made in this article uses a methodical approach towards verifying the I/O layouts by constructing pad ring based on the maximal, typical and minimal scaling factors. The need of scaling factors provides the degree of optimisation in the pad ring construction which enhances the level of verifying I/O pad layouts effectively based on the user's intent to run physical verification on the number of I/O pads in the library. The concept is developed, implemented, and verified in cadence design framework full custom environment to illustrate the effectiveness of the automation in the present industry standard. The automated physical verification is validated across several libraries and technologies to achieve significant reduction in iterative time and manual effort during the layout verification platform setup.

Keywords: I/O pad rings; input/output pads; physical verification; degree of optimisation; scaling factors; automated verification; ASIC chip design; mask layouts; layout verification.

DOI: 10.1504/IJCAD.2016.075895

International Journal of Circuits and Architecture Design, 2016 Vol.2 No.1, pp.30 - 49

Received: 25 Feb 2015
Accepted: 17 Jun 2015
Published online: 12 Apr 2016 *

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