Authors: Lin Meng; Nobuhiro Moriwaki; Shigeru Oyanagi
Addresses: Department of Electronic and Computer Engineering, Ritsumeikan University, Noji-Higashi 1-1-1, Kusatsu, Shiga, 525-8577, Japan ' College of Information Science and Engineering, Ritsumeikan University, Noji-Higashi 1-1-1, Kusatsu, Shiga, 525-8577, Japan ' College of Information Science and Engineering, Ritsumeikan University, Noji-Higashi 1-1-1, Kusatsu, Shiga, 525-8577, Japan
Abstract: Increasing instruction level parallelism is one basic way to improve the performance of superscalar processors. True data dependency is the first issue to address when it comes to increasing the performance of the processor. The chain technique, which bypasses the execution result from one arithmetic logic unit to others, is an effective method to reduce the true data dependency without using a high frequency clock. We have developed an optimal scheduling for the chain technique that uses dependency maps to store the data dependency information and utilise it to issue the chained instructions effectively. The experimental results show that the chain technique improves the performance from about 2% to 25% in CommBench and SPECint2000. The hardware configuration shows that our proposed scheduling can be implemented using just static random access memories and small-scale control logics, with no need for larger scale hardware.
Keywords: chain technique; optimal scheduling; instruction level parallelism; ILP; superscalar processors; data dependency; dependency maps.
International Journal of Advanced Mechatronic Systems, 2015 Vol.6 No.5, pp.211 - 219
Available online: 03 Nov 2015 *Full-text access for editors Access for subscribers Purchase this article Comment on this article