Title: A Si-based bulk FinFET by novel etching process with mask-less and photoresist-free lithography technique

Authors: Min-Cheng Chen; Chih-Ming Wu; Yun-Fang Hou; Yi-Ju Chen; Chang-Hsien Lin; Chia-Yi Lin; Bo-Wei Wu; Wen-Kuan Yeh

Addresses: National Applied Research Laboratories (NARL), National Nano Device Laboratories (NDL), No. 26, Prosperity Road 1, Science Park, Hsinchu City 30078, Taiwan ' National Applied Research Laboratories (NARL), National Nano Device Laboratories (NDL), No. 26, Prosperity Road 1, Science Park, Hsinchu City 30078, Taiwan ' National Applied Research Laboratories (NARL), National Nano Device Laboratories (NDL), No. 26, Prosperity Road 1, Science Park, Hsinchu City 30078, Taiwan ' National Applied Research Laboratories (NARL), National Nano Device Laboratories (NDL), No. 26, Prosperity Road 1, Science Park, Hsinchu City 30078, Taiwan ' National Applied Research Laboratories (NARL), National Nano Device Laboratories (NDL), No. 26, Prosperity Road 1, Science Park, Hsinchu City 30078, Taiwan ' National Applied Research Laboratories (NARL), National Nano Device Laboratories (NDL), No. 26, Prosperity Road 1, Science Park, Hsinchu City 30078, Taiwan ' National Applied Research Laboratories (NARL), National Nano Device Laboratories (NDL), No. 26, Prosperity Road 1, Science Park, Hsinchu City 30078, Taiwan ' National Applied Research Laboratories (NARL), National Nano Device Laboratories (NDL), No. 26, Prosperity Road 1, Science Park, Hsinchu City 30078, Taiwan

Abstract: In this study, we used maskless and photoresist-free nano injection lithography (NIL) to develop a sub-10 nm fin width for a Si-based fin field-effect transistor (FinFET) with a 50-nm fin pitch. The active layer was fabricated using double alignment technology (electron-beam lithography and NIL), and the fin trench was filled perfectly by using a high-density plasma chemical vapour deposition process. Advanced plasma and wet etching processes were employed to obtain the fin height. The fabricated FinFET could provide a pathfinding solution for the continuous scaling of complementary metal oxide semiconductor technology.

Keywords: fin FETs; field-effect transistors; FinFETs; nanoinjection lithography; sub-10 nm fin width; nanotechnology; silicon; etching process; mask-less lithography; photoresist-free lithography; electron beam lithography; plasma CVD; chemical vapour deposition; CMOS technology; continuous scaling.

DOI: 10.1504/IJNT.2015.066196

International Journal of Nanotechnology, 2015 Vol.12 No.1/2, pp.87 - 96

Published online: 04 Dec 2014 *

Full-text access for editors Access for subscribers Purchase this article Comment on this article