Authors: Amretashis Sengupta; Chandan Kumar Sarkar
Addresses: Department of Electronics & Telecommunication Engineering, Jadavpur University, Kolkata 700 032, India ' Department of Electronics & Telecommunication Engineering, Jadavpur University, Kolkata 700 032, India
Abstract: Here, we present a computational study on stacked multilayer nanoparticles embedded gate dielectric MOS non-volatile memory devices. Two device structures, one with a pure SiO2 tunnel oxide and other with a stacked HfO2-SiO2 tunnel oxide were compared. The Au nanocrystals were assumed embedded in a Si3N4 layer. The electrical parameters of the composite multilayer were evaluated using Maxwell-Garnett theory and virtual crystal approximation. From the WKB approximation, the direct and the Fowler-Nordheim tunnelling currents were evaluated, and subsequently the I-V characteristics and the flatband voltage shifts were also simulated. The flatband shift simulations were compared with recent experimental results.
Keywords: MOS; multilayer gate; nanoparticles; Fowler-Nordheim tunnelling; nanotechnology; non-volatile memory devices; nanocrystals; electrical parameters; I-V characteristics; flatband voltage shifts; simulation.
International Journal of Nanotechnology, 2014 Vol.11 No.12, pp.1073 - 1080
Published online: 14 Oct 2014 *Full-text access for editors Access for subscribers Purchase this article Comment on this article