Study on nanoparticles embedded multilayer gate dielectric MOS non-volatile memory devices
by Amretashis Sengupta; Chandan Kumar Sarkar
International Journal of Nanotechnology (IJNT), Vol. 11, No. 12, 2014

Abstract: Here, we present a computational study on stacked multilayer nanoparticles embedded gate dielectric MOS non-volatile memory devices. Two device structures, one with a pure SiO₂ tunnel oxide and other with a stacked HfO₂-SiO₂ tunnel oxide were compared. The Au nanocrystals were assumed embedded in a Si₃N₄ layer. The electrical parameters of the composite multilayer were evaluated using Maxwell-Garnett theory and virtual crystal approximation. From the WKB approximation, the direct and the Fowler-Nordheim tunnelling currents were evaluated, and subsequently the I-V characteristics and the flatband voltage shifts were also simulated. The flatband shift simulations were compared with recent experimental results.

Online publication date: Fri, 06-Feb-2015

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