Title: Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits

Authors: S. Jayanthy; M.C. Bhuvaneswari; M. Prabhu

Addresses: Department of Electronics and Communication Engineering, Sri Ramakrishna Engineering College, Coimbatore 641022, India ' Department of Electronics and Communication Engineering, Sri Ramakrishna Engineering College, Coimbatore 641022, India ' Department of Electronics and Communication Engineering, Sri Ramakrishna Engineering College, Coimbatore 641022, India

Abstract: A new multi-objective genetic algorithm has been proposed for testing crosstalk delay faults in asynchronous sequential circuits that reduces average power dissipation during test application. The proposed Elitist Non-dominated Sorting Genetic Algorithm (ENGA)-based Automatic Test Pattern Generation (ATPG) for crosstalk induced delay faults generates test pattern set that has high fault coverage and low switching activity. Redundancy is introduced in ENGA-based ATPG by modifying the fault dropping phase and hence a very good reduction in transition activity is achieved. Tests are generated for several asynchronous SIS benchmark circuits. Experimental results demonstrate that ENGA gives higher fault coverage, reduced transitions and compact test vectors for most of the asynchronous benchmark circuits when compared with those generated by Weighted Sum Genetic Algorithm (WSGA).

Keywords: asynchronous sequential circuits; crosstalk delay faults; power consumption; fault coverage; transitions; ATPG; ENGA; WSGA; simulation; redundancy; test vectors; low power testing; asynchronous circuits; genetic algorithms; automatic test pattern generation.

DOI: 10.1504/IJCAT.2013.056920

International Journal of Computer Applications in Technology, 2013 Vol.48 No.3, pp.241 - 252

Received: 08 May 2021
Accepted: 12 May 2021

Published online: 01 Oct 2013 *

Full-text access for editors Access for subscribers Purchase this article Comment on this article