Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits Online publication date: Tue, 01-Oct-2013
by S. Jayanthy; M.C. Bhuvaneswari; M. Prabhu
International Journal of Computer Applications in Technology (IJCAT), Vol. 48, No. 3, 2013
Abstract: A new multi-objective genetic algorithm has been proposed for testing crosstalk delay faults in asynchronous sequential circuits that reduces average power dissipation during test application. The proposed Elitist Non-dominated Sorting Genetic Algorithm (ENGA)-based Automatic Test Pattern Generation (ATPG) for crosstalk induced delay faults generates test pattern set that has high fault coverage and low switching activity. Redundancy is introduced in ENGA-based ATPG by modifying the fault dropping phase and hence a very good reduction in transition activity is achieved. Tests are generated for several asynchronous SIS benchmark circuits. Experimental results demonstrate that ENGA gives higher fault coverage, reduced transitions and compact test vectors for most of the asynchronous benchmark circuits when compared with those generated by Weighted Sum Genetic Algorithm (WSGA).
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