Title: Low power clock gating techniques for synchronous buffer-based queue for 3D MPSoC

Authors: Jagrit Kathuria

Addresses: Department of Electronics and Communication, H.M.R. Institute of Technology and Management, Plot No. 370, Hamidpur, New Delhi – 110036, India

Abstract: The buffer plays an important role in the design of MPSoC. The buffer mechanism influences the efficiency of link bandwidth. The buffer also provides a mechanism to synchronise the speed between the routers. The buffers are used to store packets or flits when they cannot be forwarded right away onto the output port. This paper presents discussion on buffering techniques used in the design of MPSoC. We have designed a synchronous queue for 3D MPSoC which could perform read and write operation at same time. We have generated full and AlmostFull signal to avoid overflow. The AlmostFull signal will be HIGH when one location is EMPTY to write data. The AlmostFull and full signal eliminates the overhead of sending credit information at every cycle. This reduces power dissipation from buffers. This paper presents four different low power techniques that are used to design memory for synchronous buffer-based queue.

Keywords: network on chip; NoC; buffers; clock gating; VC allocator; multiprocessor SoC; system on chip; MPSoC; synchronous queues; link bandwidth; power dissipation; memory design.

DOI: 10.1504/IJES.2013.052171

International Journal of Embedded Systems, 2013 Vol.5 No.1/2, pp.36 - 43

Received: 10 Feb 2012
Accepted: 18 Sep 2012

Published online: 15 Feb 2013 *

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