Authors: Shivam Tyagi; Mohammad Ayoub Khan
Addresses: Centre for Development of Advanced Computing, Ministry of Communications and IT, Government of India, B-30, Sector 62, Intuitional Area, Noida, UP, 201307, India ' Centre for Development of Advanced Computing, Ministry of Communications and IT, Government of India, B-30, Sector 62, Intuitional Area, Noida, UP, 201307, India
Abstract: The routing and topology has significant role to play in the design of multiprocessor system-on-chip (MPSoC). The topology has impact on the performance of the routing algorithms. As the demand is increasing for more and more area efficient devices, feature size is decreasing day-by-day. Now, the technology has reached its limitations where feature size cannot be reduced due to fundamental limitations. In such scenario, 3D ICs present a fundamental change in the SoC designs. We have investigated various 3D topologies for MPSoC. During investigation, we were unable to locate an algorithm in torus that accounts for wrap around edges. In this work, we have presented an algorithm that helps in locating wrap around edges in the torus. We have simulated the algorithm and found to be correct. As an extension of our previous work (Khan and Ansari, 2011), we have also performed net list level post layout simulation.
Keywords: network on chip; NoC; 3D topologies; 2D topologies; BDOR; torus; hyper-torus; hypercube; HTTN; symmetric; un-symmetric; multiprocessor SoC; MSoC; system on chip; SoC design; simulation.
International Journal of Embedded Systems, 2013 Vol.5 No.1/2, pp.27 - 35
Received: 06 Feb 2012
Accepted: 07 Jun 2012
Published online: 15 Feb 2013 *