Title: A new design leads to efficient bit-serial FPGA implementation for the biorthogonal 5/3 DWT filter bank

Authors: Jassim M. Abdul-Jabbar; Ahmed M. Alkababji; Dhafir A. Alneema

Addresses: Computer Engineering Department, University of Mosul, Mosul, Iraq ' Computer Engineering Department, University of Mosul, Mosul, Iraq ' Computer Engineering Department, University of Mosul, Mosul, Iraq

Abstract: In this paper, an efficient design of the lattice structure of the biorthogonal 5/3 discrete wavelet filter bank is introduced and then implemented using the technique of bit-serial implementation. This technique is usually used when area has a significant importance for the designer, where it is possible to be used for the designs that consist of similar parts of processing elements. Using VHDL language, the FPGA Spartan-3E device is exploited for implementing the designed structure. The implementation complexity (utilised chip area) of the resulting structures is significantly reduced as compared with the pipelined implementation of the same design. It also outperforms another efficient implementation of the same filter bank using lifting scheme.

Keywords: biorthogonal 5/3; lattice structure design; VHDL; bit-serial FPGA implementation; DWT filter banks; discrete wavelet transform; field programmable gate arrays.

DOI: 10.1504/IJRIS.2012.051728

International Journal of Reasoning-based Intelligent Systems, 2012 Vol.4 No.4, pp.256 - 259

Received: 08 May 2021
Accepted: 12 May 2021

Published online: 27 Jan 2013 *

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