Authors: Goran Jovanović; Mile Stojčev; Tatjana Nikolić
Addresses: Faculty of Electronic Engineering, University of Niš, Niš, Serbia. ' Faculty of Electronic Engineering, University of Niš, Niš, Serbia. ' Faculty of Electronic Engineering, University of Niš, Niš, Serbia
Abstract: As CMOS technology has scaled, supply voltage have dropped, chip power consumption has increased, and clock frequency/data rates increase effects of jitter become critical and jitter budget get tighter. Knowing how to inject/isolate jitter components with time-convolution/correlation will enhance designer ability to determine and locate the root causes. Jitter can be decomposed into several subcomponents, each having specific sets of characteristics and root causes. This paper begins with a short review of jitter fundamentals. The jitter injection technique gives test engineers an insight into how jitter components interact. In the rest of the paper a global hardware structure of a jitter generator, which uses digital techniques, based on a voltage controlled delay line is described. A Xilinx xc3s500e-5fg320 FPGA chip is used to validate this design. The programmable jitter generator can be used in jitter tolerance test for computer system and jitter transfer function measurement in communication systems.
Keywords: programmable jitter generators; jitter classification; FPGA chips; field programmable gate arrays; jitter tolerance testing; communication systems.
International Journal of Reasoning-based Intelligent Systems, 2012 Vol.4 No.1/2, pp.39 - 45
Available online: 09 Apr 2012 *Full-text access for editors Access for subscribers Purchase this article Comment on this article