Title: Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation

Authors: Imran Rafiq Quadri, Huafeng Yu, Abdoulaye Gamatie, Eric Rutten, Samy Meftali, Jean-Luc Dekeyser

Addresses: INRIA Lille Nord Europe – LIFL – USTL – CNRS, Park Plaza, 40 Avenue Halley, 56650 Villeneuve d'Ascq, France. ' IRISA/INRIA Rennes–Bretagne Atlantique, 263, Avenue du General Leclerc, 35042 Rennes, France. ' INRIA Lille Nord Europe – LIFL – USTL – CNRS, Park Plaza, 40 Avenue Halley, 56650 Villeneuve d'Ascq, France. ' INRIA Grenoble Rhone-Alpes, Inovallee, 655 Avenue de l'Europe, Montbonnot, 38344 Saint-Ismier cedex, France. ' INRIA Lille Nord Europe – LIFL – USTL – CNRS, Park Plaza, 40 Avenue Halley, 56650 Villeneuve d'Ascq, France. ' INRIA Lille Nord Europe – LIFL – USTL – CNRS, Park Plaza, 40 Avenue Halley, 56650 Villeneuve d'Ascq, France

Abstract: As SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools for handling SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach for addressing system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC co-design framework: Gaspard2. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented works are based on model-driven engineering and the UML MARTE profile proposed by object management group, for modelling and analysis of real-time embedded systems. Our contributions thus relate to presenting a complete design flow to move from high level MARTE models to automatic code generation, for implementation of dynamically reconfigurable SoCs.

Keywords: intensive signal processing; UML; MARTE; model-driven engineering; MDE; systems-on-chip; SoC co-design; adaptive systems; reconfigurability; reconfigurable FPGA; embedded systems; modelling; field programmable gate arrays.

DOI: 10.1504/IJES.2010.039025

International Journal of Embedded Systems, 2010 Vol.4 No.3/4, pp.204 - 224

Published online: 11 Mar 2011 *

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