Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation
by Imran Rafiq Quadri, Huafeng Yu, Abdoulaye Gamatie, Eric Rutten, Samy Meftali, Jean-Luc Dekeyser
International Journal of Embedded Systems (IJES), Vol. 4, No. 3/4, 2010

Abstract: As SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools for handling SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach for addressing system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC co-design framework: Gaspard2. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented works are based on model-driven engineering and the UML MARTE profile proposed by object management group, for modelling and analysis of real-time embedded systems. Our contributions thus relate to presenting a complete design flow to move from high level MARTE models to automatic code generation, for implementation of dynamically reconfigurable SoCs.

Online publication date: Fri, 11-Mar-2011

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