Title: Implications of gated-Vss technique on leakage power in embedded caches

Authors: Dhireesha Kudithipudi, Eugene John

Addresses: Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA. ' Department of Electrical and Computer Engineering, The University of Texas at San Antonio, San Antonio, Texas, USA

Abstract: In this study, we designed and implemented the gated-Vss technique on a wide range of embedded workloads and evaluated the effects of varying parameters on the static power, specifically for caches (180,130,100, and 70 nm technology nodes with a customised simulator.) The static power increased by 50% when the cache sizes were increased from 16k to 128k for L1 cache and 256k to 2M for L2 cache. Gated-Vss is an ideal solution for larger caches, especially with small latencies. Our results also indicate that the static power savings are higher when the embedded systems have dense memory operations and less misprediction rates.

Keywords: embedded systems; gated-Vss; cache leakage; nanoscale CMOS; static power savings.

DOI: 10.1504/IJES.2009.027237

International Journal of Embedded Systems, 2009 Vol.4 No.1, pp.17 - 26

Published online: 18 Jul 2009 *

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