Implications of gated-Vss technique on leakage power in embedded caches
by Dhireesha Kudithipudi, Eugene John
International Journal of Embedded Systems (IJES), Vol. 4, No. 1, 2009

Abstract: In this study, we designed and implemented the gated-Vss technique on a wide range of embedded workloads and evaluated the effects of varying parameters on the static power, specifically for caches (180,130,100, and 70 nm technology nodes with a customised simulator.) The static power increased by 50% when the cache sizes were increased from 16k to 128k for L1 cache and 256k to 2M for L2 cache. Gated-Vss is an ideal solution for larger caches, especially with small latencies. Our results also indicate that the static power savings are higher when the embedded systems have dense memory operations and less misprediction rates.

Online publication date: Sat, 18-Jul-2009

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

 
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Embedded Systems (IJES):
Login with your Inderscience username and password:

Username:        Password:          Forgotten your password?

Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email subs@inderscience.com