Title: Run-time management of custom instructions on a partially reconfigurable architecture

Authors: Siew-Kei Lam, Huang Fan, Thambipillai Srikanthan, Wu Jigang

Addresses: Centre for High Performance Embedded Systems, Nanyang Technological University, 50 Nanyang Drive, Research Techno Plaza, Border X Block, 637553 Singapore. ' Nortel Networks (China), Beijing R&D Center, D3, No. 6, Wang Jing Road East, Chaoyang District, Beijing, 100102 P.R. China. ' Centre for High Performance Embedded Systems, Nanyang Technological University, 50 Nanyang Drive, Research Techno Plaza, Border X Block, 637553 Singapore. ' Centre for High Performance Embedded Systems, Nanyang Technological University, 50 Nanyang Drive, Research Techno Plaza, Border X Block, 637553 Singapore

Abstract: Run-time reconfiguration can increase the cost efficiency and hardware specialisation of reconfigurable processors by dynamically changing the configuration of the reconfigurable logic to the required functionality. In this paper, we propose a scheme for managing the run-time reconfiguration of custom instructions on a partially reconfigurable architecture that incorporates multi-bit logic blocks. The proposed scheme relies on the dynamic execution profile to replace the functionality of the logic blocks with the goal of minimising the overall reconfiguration overhead. Experimental results show that the proposed scheme for run-time customisation can lead to an average speedup of three times and average area savings of over 30% when compared to a method that relies on compile-time customisation.

Keywords: custom instructions; embedded systems; instruction set extension; field programmable gate array; FPGA; multi-bit logic blocks; partial reconfiguration; reconfigurable architecture; reconfigurable processors; run-time management; run-time reconfiguration.

DOI: 10.1504/IJICT.2009.026429

International Journal of Information and Communication Technology, 2009 Vol.2 No.1/2, pp.50 - 59

Published online: 11 Jun 2009 *

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