Authors: Anne-Claire Guillou, Patrice Quinton, Tanguy Risset
Addresses: Irisa, Campus de Beaulieu, 35042 Rennes cedex, France. ' Irisa, Campus de Beaulieu, 35042 Rennes cedex, France. ' Universtite de Lyon, INRIA, INSA-Lyon, CITI, F69621, France
Abstract: This paper introduces methods for extending the classical systolic synthesis methodology to multi-dimensional time which implies the use of memories in the resulting architecture. Memory functions are used to define where the data are stored during execution, the targeted architecture is a distributed memory VLSI circuit. We describe a structural VHDL program for the matrix multiplication algorithm synthesised for a FPGA platform using these design principles. Our results show that the complexity added in each processor by the memories and the control is moderate and justifies in practice the use of such architectures.
Keywords: high-level synthesis; systolic architecture; multidimensional scheduling; hardware synthesis; FPGA platforms; system on chip; parallel architectures; signal processing; distributed memory VLSI circuits; structural VHDL program; matrix multiplication.
International Journal of Embedded Systems, 2008 Vol.3 No.4, pp.271 - 284
Available online: 03 Jan 2009 *Full-text access for editors Access for subscribers Purchase this article Comment on this article