Title: Investigations of silicon wafer grinding using finite element analysis

Authors: J.H. Liu, Z.J. Pei, G.R. Fisher

Addresses: Department of Industrial and Manufacturing Systems Engineering, Kansas State University, Manhattan, KS, USA. ' Department of Industrial and Manufacturing Systems Engineering, Kansas State University, Manhattan, KS, USA. ' MEMC Electronic Materials, Inc., Peters, MO, USA

Abstract: Silicon wafers are used as substrates to build more than 90% of integrated circuits. One of the manufacturing processes for silicon wafers is grinding. This paper reports the investigations of silicon wafer grinding using Finite Element Analysis (FEA). FEA models are first used to study the effects of process parameters on waviness reduction in the grinding of wire-sawn wafers on a rigid chuck. Then, soft-pad grinding of wire-sawn wafers is modelled using FEA to study the effects of pad properties on waviness reduction. Finally, FEA is used to study the elastic deformation of the grinding wheel, providing an explanation for the central dimples on ground wafers.

Keywords: dimples; finite element analysis; FEA; grinding; semiconductor material; silicon wafers; waviness removal; integrated circuits; process parameters; elastic deformation; grinding wheels.

DOI: 10.1504/IJCAT.2007.015243

International Journal of Computer Applications in Technology, 2007 Vol.29 No.2/3/4, pp.102 - 107

Published online: 30 Sep 2007 *

Full-text access for editors Access for subscribers Purchase this article Comment on this article