Investigations of silicon wafer grinding using finite element analysis
by J.H. Liu, Z.J. Pei, G.R. Fisher
International Journal of Computer Applications in Technology (IJCAT), Vol. 29, No. 2/3/4, 2007

Abstract: Silicon wafers are used as substrates to build more than 90% of integrated circuits. One of the manufacturing processes for silicon wafers is grinding. This paper reports the investigations of silicon wafer grinding using Finite Element Analysis (FEA). FEA models are first used to study the effects of process parameters on waviness reduction in the grinding of wire-sawn wafers on a rigid chuck. Then, soft-pad grinding of wire-sawn wafers is modelled using FEA to study the effects of pad properties on waviness reduction. Finally, FEA is used to study the elastic deformation of the grinding wheel, providing an explanation for the central dimples on ground wafers.

Online publication date: Sun, 30-Sep-2007

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