Title: Low area FPGA implementation of modified histogram estimation architecture with CSAC-DPROM-OBC for medical image enhancement application

Authors: Koteswar Rao Bonagiri; Giri Babu Kande; P. Chandrasekhar Reddy

Addresses: Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, 500085 Hyderabad, India; Marrilaxman Reddy Institute of Technology and Management, 500043 Telangana, India ' Department of Electronics and Communication Engineering, Vasireddy Venkatadri Institute of Technology, 522508 Andhrapradesh, India ' Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, 500085 Hyderabad, India

Abstract: In this work, modified histogram estimation (MHE) architecture is proposed to verify the histogram count in the FPGA platform, and the Basic HE (BHE) architecture is also implemented for comparative purpose. The entire proposed MHE architecture is developed newly so as to reduce the logical elements involved in the HE process. In MHE architecture, dual port read only memory (DPROM), carry select adder based counter (CSAC), and Optimal Bin Counter (OBC) are used to evaluate the HE count with effective accuracy. The amount of percentage reduced by the 256 sample MHE is 17.62%, 15.41% and 23.01% for area, power and delay respectively. Additionally, the performance of the proposed MHE is compared with four existing methods HOG, HBS, MBPA and DMH. The number of flip flops utilised by the MHE architecture is 2177 for Vertex 6 device, which is less compared to the HOG and MBPA.

Keywords: area; basic histogram estimation; CSAC; carry select adder based counter; delay; DPROM; dual port read only memory; field programmable gate array; medical image enhancement; MHE; modified histogram estimation; optimal bin counter; power.

DOI: 10.1504/IJNT.2023.131116

International Journal of Nanotechnology, 2023 Vol.20 No.1/2/3/4, pp.259 - 280

Received: 02 Nov 2021
Accepted: 31 Dec 2021
Published online: 31 May 2023 *