Title: Design and analysis of tri-layered strained channel HOI CGAA FET

Authors: Rasmita Barik; Kuleen Kumar; Rudra Sankar Dhar

Addresses: Department of Electronics and Communication Engineering, National Institute of Technology Mizoram, Aizawl – 796012, India ' Department of Electronics and Communication Engineering, National Institute of Technology Mizoram, Aizawl – 796012, India ' Department of Electronics and Communication Engineering, National Institute of Technology Mizoram, Aizawl – 796012, India

Abstract: Introducing three ultrathin-strained layers in the channel forming heterostructure-on-insulator (HOI) cylindrical gate-all-around (CGAA) FET is the requisite at nano regime. The outermost-layer and the central-layer of the CGAA is strained silicon (s-Si) while the middle-layer sandwiched between the two s-Si layers is strained silicon germanium (s-SiGe). Congealing the channel with these strained layers quantum carrier confinement prompts enhances the carrier mobility and counter threshold voltage roll-off. The tri-layer HOI device enhances device performance in comparison to conventional silicon CGAA. The newly developed CGAA at 22 nm gate length displays 20.6% enhancement in on-current in comparison to silicon CGAA. Further analysis of the novel device shows 92% and 80.2% improvement in I_on/I_off ratio as compared to silicon CGAA and strained channel rectangular GAA, respectively. The CGAA also provided 16.2% augmentation on drain current as compare to 22 nm strained silicon channel rectangular GAA FET.

Keywords: carrier mobility; carrier confinement; current density; electric field.

DOI: 10.1504/IJNP.2022.126375

International Journal of Nanoparticles, 2022 Vol.14 No.2/3/4, pp.138 - 146

Received: 24 Aug 2021
Accepted: 09 Feb 2022
Published online: 24 Oct 2022 *

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