Title: A novel design of a 1 GHz phase locked loop with improved lock time for fast frequency acquisition
Authors: Monika Bhardwaj; Sujata Pandey; Neeta Pandey
Addresses: Department of ECE, Amity School of Engineering and Technology, Amity University, Noida, UP, India ' Department of ECE, Amity School of Engineering and Technology, Amity University, Noida, UP, India ' Department of ECE, Delhi Technological University, Delhi, India
Abstract: This paper contains a low power PLL with better lock time which involves the designing of charge pump, voltage-controlled oscillator, loop filter, and phase frequency detector at low power. Logical expressions are developed and analysed for the parameters of system design. System related noise model is also presented for output and internal noise. The PLL is designed to offer high speed performance at low cost. Loop filter design is the most important block in designing low noise and low cost device, which helps in improving the overall system performance. The PLL is designed using 0.18 um CMOS process in Tanner design tool and 1.8 v supply. It is designed to operate in the frequency range of 200 MHz-1 GHz which is used to generate the clock signals where the input frequency signal is synchronised. The designed PLL can be used in variety of frequency synthesisers in the field of communication and instrumentation.
Keywords: phase locked loop; PLL; VCO; charge pump; CP; phase error; phase frequency detector; PFD; channel length modulation.
International Journal of Computer Aided Engineering and Technology, 2022 Vol.17 No.2, pp.192 - 207
Received: 05 Sep 2019
Accepted: 06 Jan 2020
Published online: 24 Aug 2022 *