A novel design of a 1 GHz phase locked loop with improved lock time for fast frequency acquisition Online publication date: Wed, 24-Aug-2022
by Monika Bhardwaj; Sujata Pandey; Neeta Pandey
International Journal of Computer Aided Engineering and Technology (IJCAET), Vol. 17, No. 2, 2022
Abstract: This paper contains a low power PLL with better lock time which involves the designing of charge pump, voltage-controlled oscillator, loop filter, and phase frequency detector at low power. Logical expressions are developed and analysed for the parameters of system design. System related noise model is also presented for output and internal noise. The PLL is designed to offer high speed performance at low cost. Loop filter design is the most important block in designing low noise and low cost device, which helps in improving the overall system performance. The PLL is designed using 0.18 um CMOS process in Tanner design tool and 1.8 v supply. It is designed to operate in the frequency range of 200 MHz-1 GHz which is used to generate the clock signals where the input frequency signal is synchronised. The designed PLL can be used in variety of frequency synthesisers in the field of communication and instrumentation.
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Computer Aided Engineering and Technology (IJCAET):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email subs@inderscience.com
Our Blog 
Follow us on Twitter 
Visit us on Facebook