Title: Efficient hardware implementation of TEA, XTEA and XXTEA lightweight ciphers for low resource IoT applications

Authors: Zeesha Mishra; Bibhudendra Acharya

Addresses: Department of Electronics and Communication Engineering, National Institute of Technology Raipur, Chhattisgarh, CG, 492010, India ' Department of Electronics and Communication Engineering, National Institute of Technology Raipur, Chhattisgarh, CG, 492010, India

Abstract: Among instances when the data security in resource constrained environment is taken into consideration, lightweight encryption algorithms admit in popularity and are deemed to be of great merit. Reduction of both power consumption and area are always a major concern. Tiny encryption algorithm (TEA) is one of the lightweight cryptographic algorithm with block size of 64-bit and key size of 128-bit follows Feistel network structure and further this algorithm is modified as extended tiny encryption algorithm (XTEA) and Corrected tiny encryption algorithm (XXTEA). This paper have proposed highly efficient round-based architectures of TEA, XTEA and XXTEA to make them suitable for the low area, low power applications. The strategy is to optimise the hardware design for low resource applications. All the three proposed architectures are extensively evaluated and compared on the basis of performance, and area utilisation for their implementations in different field-programmable gate array (FPGA) platforms.

Keywords: IoT; Internet of Things; lightweight cryptography; TEA algorithm; XTEA algorithm; Fiestel structure; FPGA; field-programmable gate array; throughput; slices.

DOI: 10.1504/IJHPSA.2021.119150

International Journal of High Performance Systems Architecture, 2021 Vol.10 No.2, pp.80 - 88

Received: 21 May 2020
Accepted: 18 Mar 2021
Published online: 25 Nov 2021 *

Full-text access for editors Full-text access for subscribers Purchase this article Comment on this article