Title: A CAD approach for power supply noise aware floorplan in SoC

Authors: Partha Mitra; Jaydeb Bhaumik; Angsuman Sarkar

Addresses: Department of Electronics and Communication Engineering, Maulana Abul Kalam Azad University of Technology, West Bengal, Haringhata-741249, India ' Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata-700032, India ' Department of Electronics and Communication Engineering, Kalyani Government Engineering College, Kalyani-741235, India

Abstract: This paper deals for reduction of power supply noise with decoupling capacitor estimation and allocation using particle swarm optimisation (PSO) algorithm at the floorplanning stage of the physical design process. Decoupling capacitors are allocated between the power and ground rails in parallel with functional blocks having supply noise effectively reduces rapid fluctuations in supply voltage. Excess capacitors increases the delay and power parameters and degrades the overall performance of the integrated circuit. In this work peak supply noise has been reduced by up to 69.5%, increment in delay and power parameters is 6.52% and 2.08% with decoupling capacitor allocation. Maximum increment in core area is 6.57% with decoupling capacitor allocation. The decoupling capacitor (decap) budget has also been optimised by up to 36.7%. This computer aided design (CAD) approach can be used power supply noise reduction for any multi-core architecture.

Keywords: CAD; computer aided design; decap; decoupling capacitor; PSO; particle swarm optimisation; PDN; power distribution network; SoC; system-on-chip; WS; white space.

DOI: 10.1504/IJHPSA.2021.119148

International Journal of High Performance Systems Architecture, 2021 Vol.10 No.2, pp.64 - 69

Received: 30 Sep 2020
Accepted: 30 Jan 2021
Published online: 25 Nov 2021 *

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