Authors: Aastha Modgil; Vivek Kumar Sehgal; Nitin Chanderwal
Addresses: Department of CSE and IT, Jaypee University of Information Technology, Waknaghat, Solan, 173234, HP, India ' Department of CSE and IT, Jaypee University of Information Technology, Waknaghat, Solan, 173234, HP, India ' Department of Electrical Engineering and Computer Science, University of Cincinnati, Cincinnati, 45219, Ohio, USA
Abstract: In a chip multiprocessor (CMP) major resource that is being shared among multiple cores is main memory as it is responsible for storing data structures needed for execution of a program. Diverse threads running simultaneously on same chip may compete with each other for resources. Because of interference among threads, each thread can experience extremely different memory system performance. If interference among threads is not controlled, then one thread can experience extreme slowdown while another is unfairly prioritised. By efficiently reordering concurrent memory requests, power consumption and thread fairness can be improved. This work proposes a memory access scheduler, energy-efficient fairness-aware (EEFA) memory access scheduling that provides thread fairness, exploits bank level parallelism by pre-issuing issuable read commands during drain-write mode. Also, proposed scheduler prioritises row buffer hit requests. The authors show that EEFA memory access scheduling significantly reduces unfairness among threads and energy consumption in DRAM memory system while also improving performance.
Keywords: DRAM; energy efficiency; thread fairness; bank level parallelism; row buffer hit; memory access scheduling; chip multiprocessor; CMP.
International Journal of Services Technology and Management, 2020 Vol.26 No.6, pp.520 - 537
Received: 07 Jan 2017
Accepted: 05 Feb 2018
Published online: 01 May 2020 *