Title: An improved topology of cascaded multilevel inverter with low switch count

Authors: Bikram Das; Manas Patra; Debashis Chatterjee; Aniruddha Bhattacharya

Addresses: Department of Electrical Engineering, NIT Agartala, Jirania, Barjala, Tripura West, 799046, India ' Department of Electrical Engineering, NIT Agartala, Jirania, Barjala, Tripura West, 799046, India ' Department of Electrical Engineering, Jadavpur University, Kolkata, West Bengal, 700032, India ' Department of Electrical Engineering, NIT Agartala, Jirania, Barjala, Tripura West, 799046, India

Abstract: An improved topology of the multilevel inverter is described in this paper. Proposed topology is comprised of the basic module to get positive levels at the output. An H-bridge can be formed to obtain ac output. Developed topology significantly reduces the number of IGBTs, DC voltage sources, gate drivers for the same number of levels. Different algorithms are presented to determine the number of levels, switches, total blocking voltage and total standing voltage. Comparison of the proposed topology with the conventional cascaded multilevel inverters and other existing topologies in the literature has been carried out to show the advantages of the newly proposed topology. The operation and performance of the proposed multilevel inverter are verified by suitable experimental results with a single phase 15-level multilevel inverter considering resistive and inductive loads.

Keywords: cascaded multilevel inverter; reduced switch; loss comparison; total standing voltage; TSV; H-bridge.

DOI: 10.1504/IJPELEC.2020.108383

International Journal of Power Electronics, 2020 Vol.12 No.1, pp.1 - 29

Received: 13 Aug 2017
Accepted: 03 Feb 2018
Published online: 13 Jul 2020 *

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