An improved topology of cascaded multilevel inverter with low switch count
by Bikram Das; Manas Patra; Debashis Chatterjee; Aniruddha Bhattacharya
International Journal of Power Electronics (IJPELEC), Vol. 12, No. 1, 2020

Abstract: An improved topology of the multilevel inverter is described in this paper. Proposed topology is comprised of the basic module to get positive levels at the output. An H-bridge can be formed to obtain ac output. Developed topology significantly reduces the number of IGBTs, DC voltage sources, gate drivers for the same number of levels. Different algorithms are presented to determine the number of levels, switches, total blocking voltage and total standing voltage. Comparison of the proposed topology with the conventional cascaded multilevel inverters and other existing topologies in the literature has been carried out to show the advantages of the newly proposed topology. The operation and performance of the proposed multilevel inverter are verified by suitable experimental results with a single phase 15-level multilevel inverter considering resistive and inductive loads.

Online publication date: Mon, 13-Jul-2020

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