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Title: A comparative study on the effects of technology nodes and logic styles for low power high speed VLSI applications

Authors: Inamul Hussain; Saurabh Chaudhury

Addresses: Department of Electrical Engineering, National Institute of Technology, Silchar, Assam, 788010, India ' Department of Electrical Engineering, National Institute of Technology, Silchar, Assam, 788010, India

Abstract: Carbon nanotubes (CNT) field-effect transistor (CNTFET) could be a possible alternative to CMOS technology for future VLSI applications. In this work, a comparative study has been carried out on the effects of technology nodes and logic styles on power dissipation, delay, leakages, etc. The technology nodes that are considered here are 90 nm and 32 nm MOSFET technology, and 32 nm CNTFET technology. The logic families considered here are the conventional complementary metal-oxide-semiconductor (CMOS), complementary pass transistor logic (CPL) and transmission gate (TG). The digital circuits considered are NAND, NOR, XOR and MUX gates. HSPICE simulations have been carried out and observed that at 32 nm CNTFET technology, the least power, worst-case delay and least PDP are found as 15.5 nW, 3.11 ps and 0.048 aJ, respectively. It is witnessed that CNTFET-based logics are superior compared to other logic families at different technology nodes.

Keywords: logic styles; complementary metal oxide semiconductor; CMOS; complementary pass transistor logic; CPL; transmission gate; TG; power delay product; PDP; CNTFET.

DOI: 10.1504/IJNP.2020.106004

International Journal of Nanoparticles, 2020 Vol.12 No.1/2, pp.122 - 135

Received: 15 Jan 2019
Accepted: 19 Jul 2019

Published online: 20 Mar 2020 *

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