Title: Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm
Authors: Aniruddha Ghosh; Amitabha Sinha
Addresses: ECE Department, Calcutta Institute of Technology, Uluberia, Howrah, WB, India ' Birbhum Institute of Engineering and Technology, Suri, Birbhum, WB, India
Abstract: Today, the complication of binary digital hardware system is progressively growing. Due to this fact, new methodologies for efficiently describing and realising the digital systems are explored in this paper. Multi-valued logic methodology offers a few preferences over existing binary digital system. One of the well-known multi-valued logic systems is ternary value logic (TVL) system. It is seen that all kind of digital signal processing (DSP) algorithms widely use multiply-accumulate (MAC) operation for superior digital processing system. To implement high performance DSP algorithms MAC unit is used extensively. In current scenario, it is seen that non-conventional, non-binary number system-based architecture is also exhibited better performance. The example of such non-conventional, non-binary number systems is ternary residue number systems (TRNSs) and double base ternary number system (DBTNS). Here, a comparative study is made on performance analysis of MAC unit using various non-conventional, non-binary number system. All the architecture is mapped on FPGA for analysis its performance.
Keywords: ternary value logic; TVL; ternary residue number systems; TRNSs; TRNS adder; DBTNS; field programmable gate array; FPGA; DSP algorithms; multiply and accumulate unit; MAC; DBTNS multiplier.
International Journal of Nanoparticles, 2020 Vol.12 No.1/2, pp.50 - 58
Received: 26 Jan 2019
Accepted: 24 Jun 2019
Published online: 20 Mar 2020 *