Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm
by Aniruddha Ghosh; Amitabha Sinha
International Journal of Nanoparticles (IJNP), Vol. 12, No. 1/2, 2020

Abstract: Today, the complication of binary digital hardware system is progressively growing. Due to this fact, new methodologies for efficiently describing and realising the digital systems are explored in this paper. Multi-valued logic methodology offers a few preferences over existing binary digital system. One of the well-known multi-valued logic systems is ternary value logic (TVL) system. It is seen that all kind of digital signal processing (DSP) algorithms widely use multiply-accumulate (MAC) operation for superior digital processing system. To implement high performance DSP algorithms MAC unit is used extensively. In current scenario, it is seen that non-conventional, non-binary number system-based architecture is also exhibited better performance. The example of such non-conventional, non-binary number systems is ternary residue number systems (TRNSs) and double base ternary number system (DBTNS). Here, a comparative study is made on performance analysis of MAC unit using various non-conventional, non-binary number system. All the architecture is mapped on FPGA for analysis its performance.

Online publication date: Tue, 24-Mar-2020

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