Title: Partial product generation for unbalanced ternary signed multiplication

Authors: Samira Din Mohammadi; Reza Faghih Mirzaee; Keivan Navi

Addresses: Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran 37515-374, Iran ' Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran 37515-374, Iran ' Faculty of Computer Science and Engineering, Shahid Beheshti University, G.C., Tehran 1983969411, Iran

Abstract: Signed multiplication is an essential operation in computer arithmetic. The first step of multiplication is called partial product generation. Partial products are simply generated in binary logic by 'AND'ing every bit of multiplier with the bits of multiplicand. No matter that the numbers are signed or unsigned, AND is the partial product generator in binary logic. However, the same process in ternary logic is not as simple as in binary. The AND gate loses its efficiency. The employment of an ordinary 1-digit ternary multiplier is not sufficient either since it only multiplies two positive ternary digits. New ternary operators are required for the multiplication of negative digits. This paper presents these operators for the unbalanced ternary signed multiplier. The proposed operators are realised with three different well-known ternary circuit topologies by 32 nm CMOS technology.

Keywords: Baugh-Wooley multiplication; computer arithmetic; partial product generation; ternary signed multiplier; ternary logic; negative partial product; partial product reduction; ternary operator; transistor-level design; multiple-valued logic.

DOI: 10.1504/IJHPSA.2019.104952

International Journal of High Performance Systems Architecture, 2019 Vol.8 No.4, pp.238 - 249

Received: 24 Oct 2019
Accepted: 31 Oct 2019
Published online: 07 Feb 2020 *

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