Partial product generation for unbalanced ternary signed multiplication Online publication date: Fri, 07-Feb-2020
by Samira Din Mohammadi; Reza Faghih Mirzaee; Keivan Navi
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 8, No. 4, 2019
Abstract: Signed multiplication is an essential operation in computer arithmetic. The first step of multiplication is called partial product generation. Partial products are simply generated in binary logic by 'AND'ing every bit of multiplier with the bits of multiplicand. No matter that the numbers are signed or unsigned, AND is the partial product generator in binary logic. However, the same process in ternary logic is not as simple as in binary. The AND gate loses its efficiency. The employment of an ordinary 1-digit ternary multiplier is not sufficient either since it only multiplies two positive ternary digits. New ternary operators are required for the multiplication of negative digits. This paper presents these operators for the unbalanced ternary signed multiplier. The proposed operators are realised with three different well-known ternary circuit topologies by 32 nm CMOS technology.
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