Title: Design and implementation of LTE physical layer on FPGA

Authors: V. Venkataramanan; S. Lakshmi; Vineet A. Kanetkar

Addresses: Department of Electronics and Communication, School of Electrical and Electronics Engineering, Sathyabama Institute of Science and Technology, Sholinganallur, Chennai-119, Tamil Nadu, India ' Department of Electronics and Communication, School of Electrical and Electronics Engineering, Sathyabama Institute of Science and Technology, Sholinganallur, Chennai-119, Tamil Nadu, India ' Department of Electronics and Telecommunication, Dwarakadas J. Sanghvi College of Engineering, Mumbai-56, Maharashtra, India

Abstract: Changing trends in the communication industry pertaining to configuration of devices and their processing for maximised result. Each device needs a processing unit comprising a microcontroller or a Field Programmable Gate Array (FPGA). This paper deals with the use of FPGAs and how they can be configured as Hardware in Loop (HIL) for validation along with Simulink and Xilinx System Generator (XSG). Further, their compatibility is mentioned for long term use and durability in communication. The comparison of related work in the field of communication is done with the FPGA implementation of Long Term Evolution (LTE) physical layer with different modulation schemes, different antenna configurations and different signal to noise ratio systems implemented on Virtex and Spartan FPGA boards. On the other hand the simulation is carried out with Xilinx Vivado Design suite to analyse the power, resource utilisation, timing summary and memory utilisation.

Keywords: field programmable gate array; hardware co-simulation; LTE; MIMO; OFDM; 3GPP.

DOI: 10.1504/IJCAT.2019.102111

International Journal of Computer Applications in Technology, 2019 Vol.61 No.1/2, pp.127 - 134

Received: 13 Sep 2018
Accepted: 19 Oct 2018
Published online: 06 Sep 2019 *

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